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Description: 并口的CPLD烧录线,通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
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Size: 2302730 |
Author: mikeldm@163.com |
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Description: 包括XILINX的FPGA、CPLD、IP、工具、开发板等
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Size: 404947 |
Author: zheng_wb@sina.com |
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Description: Interface 8051 to Coolrunner CPLD(Xilinx App)
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Size: 22528 |
Author: 高威 |
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Description: XilinxJTAG.rar
xilinx CPLD,FPGA的JTAG口使用说明.-XilinxJTAG.rar Xilinx CPLD, FPGA JTAG I use.
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Size: 431104 |
Author: |
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Description: xilinx xc9572 cpld 实现的伺服电机控制器,电机控制输出,和增量编码器读取。-Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.
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Size: 797696 |
Author: 张宏亚 |
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Description: yon用硬件描述语言写的曼彻斯特编解码,并在Xilinx CPLD上的实现,内容齐全,是学习的好资料-yon hardware description language used to write the Manchester encoding and decoding Xilinx CPLD and the realization that the complete study is a good information
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Size: 10240 |
Author: slam |
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Description: 3倍频实用稳定算法的VHDL实现(XILINX CPLD)-3 octave practical VHDL realize stable algorithm (XILINX CPLD)
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Size: 2048 |
Author: sean |
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Description: \fpga cpld\XILINXCPLD-JTAG \fpga cpld\XILINXCPLD-JTAG
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Size: 63488 |
Author: 张孝贤 |
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Description: 在文件夹YL2440_CPLD中有做好的CPLD工程,请用Xilinx ISE 6.2打开.-In the folder have to do a good job YL2440_CPLD the CPLD project, please open the Xilinx ISE 6.2.
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Size: 686080 |
Author: gaofeng |
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Description: MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
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Size: 64512 |
Author: sq |
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Description: 利用XC9572-TQFP100(Xilinx CPLD)制作的多功能CPLD/FPGA的ISP下载线源代码及线路图。可用来烧录Xilinx,Lattice,Altera等厂家的CPLD/FPGA.-Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilinx, Lattice, Altera and other manufacturers of the CPLD/FPGA.
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Size: 3234816 |
Author: 李德明 |
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Description: 利用Xilinx XC2C128(Xilinx CPLD)制做的台式电脑的Debug卡及原理图,对于不开机的主板,能侦测出CPU到北桥之间具体那根信号线空焊,用于快速维修不开机之主板。-The use of Xilinx XC2C128 (Xilinx CPLD) desktop computer system to do the Debug Card and schematic diagram for the motherboard does not boot, can detect the CPU to the Northbridge Flanagan signal line between the concrete and air welding, maintenance for fast boot the motherboard.
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Size: 1223680 |
Author: 李德明 |
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Description: 利用XC9572-PQ44(Xilinx CPLD)制作的一款家用防盗报警器的Verilog源代码及原理图,当房门打开后,15秒内若没有按下Key1,则会自动拨打设定手机号(当然,要另连接一台手机)-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15 seconds if there is no pressing Key1, will be set automatically dial the phone number (of course, Another connection to a mobile phone)
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Size: 918528 |
Author: 李德明 |
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Description: LCD Interface_Xilinx.CPLD源码参考设计-LCD Interface Xilinx CPLD
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Size: 1978368 |
Author: huangxing |
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Description: 配置快速入门指南本应用指南讨论 Xilinx 的复杂可编程逻辑器件 (CPLD)、现场可编程门阵列 (FPGA) 和 PROM 系
列的配置与编程选项,并演示了各系列最常用的部分配置方法。-xilinx c_xapp501 spec
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Size: 549888 |
Author: 小王王 |
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Description: Schematics and PCB Layout for a small Xilinx 95xx CPLD development board.
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Size: 234496 |
Author: AleMaxx |
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Description: Xilinx公司的CPLD芯片选型指南 CPLD芯片选型指南-Xilinx CPLD chip Selection Guide
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Size: 2182144 |
Author: liShengyi |
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Description: 简要介绍:
主要芯片:
CPU:ATmega128L
SRAM:SR61L256BS-8
CPLD:XILINX XC95144XL
SFLASH:AT45DB081B
ETHERNET:CS8900A
USB:PDIUSBD12
LCD:122x32 LMC62_095_M
POWER:LM2596S-3.3
RS232:MAX3232
软件:RS232,SRAM,CPLD调试通过,uCosII可以运行,ethernet部分没有完成,usb完成了一部分。 -HD MP3 USE MEGA128
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Size: 11170816 |
Author: shi |
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Description: Xilinx-CPLD开发板CPLD开发套件说明书-Xilinx-CPLD development board CPLD Development Kit manual
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Size: 1433600 |
Author: huguangzhou |
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Description: 本应用笔记讨论的是Xilinx 的复杂可编程器件(CPLD)、现场可编程门阵列(FPGA)和PROM系列的配置和编程选项。它示意了每个系列的最常用的一些配置方法。-This application note of the discussion is the complex programmable device Xilinx (CPLD), field programmable gates array (FPGA) and PROM series of configuration and programming options. It found each series of some of the most common configuration method.
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Size: 353280 |
Author: 崔健 |
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